Senior Principal Ic Design Verification Application Engineer
Cadence
Base: $143,500 to $266,500 (california); bonus/equ...
Systemverilog vhdl verilog verification skills
Uvm testbench architecture development and debug
Strong rtl and testbench debug skills
This role involves working directly with industry-leading semiconductor companies to deploy Cadence's market-leading verification platforms including cutting-edge technologies using AI assistants
Job Summary
This role involves working directly with industry-leading semiconductor companies to deploy Cadence's market-leading verification platforms including cutting-edge technologies using AI assistants.
The ideal candidate will provide front-line technical support in the pre- and post-sales process while developing customer-specific verification requirements and methodologies.
Employees are eligible for incentive compensation including bonus and equity, along with comprehensive benefits such as a 401(k) plan with employer match and medical coverage.
Matching Summary
This role involves working directly with industry-leading semiconductor companies to deploy Cadence's market-leading verification platforms including cutting-edge technologies using AI assistants.
Salary
Base: $143,500 to $266,500 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, holidays, 401(k) match, stock purchase plan
Skills & Requirements
Must-have
SystemVerilog VHDL Verilog verification skills
UVM testbench architecture development and debug
Strong RTL and Testbench debug skills
Scripting experience in Perl Python or Tcl
7+ years experience in hardware verification
Nice-to-have
Experience with C/C++ SystemC
Knowledge of JTAG UART PCIe AMBA DDR protocols
Familiarity with AI assistants and Agentic AI
Ability to create technical product literature
Strong verbal and written communication skills
Key Requirements
BS MS or PhD in Computer Science Engineering or related field
Minimum 7 years of professional verification experience
Proficiency in UVM testbench architecture and debugging