This role involves modeling and simulating high-speed links including SerDes, IC packages, and system interconnects for next-generation platforms
Job Summary
This role involves modeling and simulating high-speed links including SerDes, IC packages, and system interconnects for next-generation platforms.
The successful candidate will lead pre- and post-layout signal integrity analysis while defining stack-up strategies and collaborating with vendors on manufacturability.
You will mentor junior engineers and drive the SI/PI technology roadmap by evaluating emerging tools and design paradigms alongside top industry talent.
Matching Summary
This role involves modeling and simulating high-speed links including SerDes, IC packages, and system interconnects for next-generation platforms.
Skills & Requirements
Must-have
12+ years Signal Power Integrity experience
VNA TDR oscilloscope measurement skills
HFSS ADS Allegro simulation tools expertise
SerDes IC package PCB system modeling
Power delivery network analysis
Nice-to-have
PAM4 SerDes knowledge
Co-packaged optics familiarity
Mentorship and team leadership skills
Optical transceiver module experience
Continuous improvement mindset
Key Requirements
BSEE degree required or MSEE with 10+ years experience
Strong fundamentals in electromagnetics and transmission line theory
Hands-on experience with VNA, TDR, and high-bandwidth oscilloscopes