Technical Lead Digital Design Engineer

Astera Labs

Toronto, Canada
Base: $140,000 cad - $175,000 cad; bonus/equity: n...
On-site
High-performance pcie controller and bridge design
Rtl development and synthesis
Ip integration for serdes and controller ips
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, enabling organizations to unlock the full potential of modern AI

Job Summary

  • Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, enabling organizations to unlock the full potential of modern AI.
  • The Technical Lead Digital Design Engineer will be responsible for designing and implementing high-performance digital solutions, including RTL development and synthesis, and collaborating with cross-functional teams on IP integration.
  • The role requires ownership of block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm, and ensuring timing closure and verification completeness.

Matching Summary

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, enabling organizations to unlock the full potential of modern AI.

Salary

Base: $140,000 CAD - $175,000 CAD; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • High-performance PCIE controller and bridge design
  • RTL development and synthesis
  • IP integration for Serdes and Controller IPs
  • System Verilog/Verilog and scripting (Python/Perl)
  • Pre-silicon and post-silicon design implementation
  • FW interaction and embedded design

Nice-to-have

  • Working in design and verification workflows in a CI/CD environment
  • NIC, switch, or storage product development
  • PAD design, DFT, and floor planning

Key Requirements

  • Bachelor’s in Electronics/Electrical engineering (Master's preferred)
  • 5+ years of digital design experience
  • 4+ years focused on PCIE controller, PCS or PHY implementation
  • Proven expertise in RTL development, synthesis, and timing closure
  • Experience with front-end design, gate-level simulations, and design verification
  • Experience with block-level and full-chip design at advanced nodes (≤ 16nm)
  • Top level integration and DFT knowledge

Work Rights

Not specified

Tailored Resume

Cover Letter