Logic optimization for power, performance, area, timing
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Job Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block.
Matching Summary
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Skills & Requirements
Must-have
RTL design with Verilog and/or VHDL
IP block integration and verification
Logic optimization for power, performance, area, timing
Nice-to-have
Strong communication and teamwork skills
Highly motivated to learn and adapt
Promotes innovation and initiative
Key Requirements
Bachelors or Master’s degree in EE, CE or CS, or equivalent
Experienced using advanced verification methodologies
Familiarity or experience with RTL verification and timing analysis/closure