Asic Dft Engineer

Broadcom

San Jose, California, United States
Base: $141,300 - $226,000; bonus/equity: discretio...
Dft architecture and implementation
Scan insertion and compression
Atpg vector generation and debugging
The successful candidate will lead DFT programs from chip level specification through implementation and verification to product release

Job Summary

  • The successful candidate will lead DFT programs from chip level specification through implementation and verification to product release.
  • Broadcom offers a competitive salary range, discretionary annual bonus, equity awards, and a comprehensive benefits package including medical, dental, vision, 401(K) with company matching, and paid leave.
  • The role involves working closely with cross-functional teams and customers globally to improve test coverage, silicon yield, and debug returned parts.

Matching Summary

The successful candidate will lead DFT programs from chip level specification through implementation and verification to product release.

Salary

Base: $141,300 - $226,000; Bonus/Equity: Discretionary annual bonus and equity awards; Benefits: Medical, dental, vision, 401(K) matching, ESPP, paid leave

Skills & Requirements

Must-have

  • DFT Architecture and implementation
  • Scan insertion and compression
  • ATPG vector generation and debugging
  • Memory BIST insertion and verification
  • Test vector generation and validation
  • Silicon bring-up and debug
  • Cross-functional collaboration

Nice-to-have

  • Experience with Serdes, DDR, PCIE, ENET, CXL
  • Experience with Tessent SSN
  • Project management capabilities
  • Strong problem solving and communication skills
  • Automation of DFT and test vector flows
  • Knowledge of IEEE standards 1149.1, 1149.6, 1687

Key Requirements

  • Bachelors with 12+ years experience or Masters with 10+ years experience
  • Strong DFT background including IO and Analog DFT, ATPG, Scan, BIST
  • Experience with DFT Compiler and Mentor TestKompress
  • Proficiency in Verilog coding and testbench simulation
  • Knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG
  • Experience with silicon failure analysis and yield improvement

Work Rights

Not specified

Tailored Resume

Cover Letter