The IC Layout Engineer position within the High Performance Analog (HPA) division is responsible for developing and verifying integrated-circuit (IC) layouts in close collaboration with design engineers, supporting programs from initial floorplanning through tapeout
Job Summary
The IC Layout Engineer position within the High Performance Analog (HPA) division is responsible for developing and verifying integrated-circuit (IC) layouts in close collaboration with design engineers, supporting programs from initial floorplanning through tapeout.
The position uses industry-standard EDA tools to complete schematic capture, physical verification (DRC/LVS), and documentation in support of GaAs, Silicon, and GaN technologies.
This is a hybrid position where the expectation is to be onsite in our Richardson TX office a minimum of four days a week.
Matching Summary
The IC Layout Engineer position within the High Performance Analog (HPA) division is responsible for developing and verifying integrated-circuit (IC) layouts in close collaboration with design engineers, supporting programs from initial floorplanning through tapeout.
Skills & Requirements
Must-have
IC layout development and verification
Schematic capture and physical verification
Keysight ADS experience
GaAs, Silicon, and GaN technologies
Hybrid work model (4 days onsite)
Nice-to-have
Attention to detail and high-quality deliverables
Working knowledge of Windows and Linux
Strong analytical and collaboration skills
Key Requirements
Bachelor’s degree in Electrical Engineering or related field