Silicon Packaging Design Engineer

Intel

Phoenix, Arizona, United States
Base: $105,650.00-149,150.00 usd; bonus/equity: st...
Substrate design rules
Physical layout and routing
Microelectronic package physical layout
Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements

Job Summary

  • Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
  • Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability and performance.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.

Salary

Base: $105,650.00-149,150.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • Substrate design rules
  • Physical layout and routing
  • Microelectronic package physical layout
  • PCB physical layout design
  • Package I/O routing

Nice-to-have

  • Creative problem-solving skills
  • Scripting using Python, VB, C
  • Electrical modeling and simulation tools

Key Requirements

  • Bachelors with 1+ years of experience or Master's with 6 months experience
  • 6+ months experience with microelectronic package or PCB physical layout design
  • Familiarity with package design tools

Work Rights

Not specified

Tailored Resume

Cover Letter