Physical Design Timing Engineer

Inteelabs

Bangalore, India
Physical design timing analysis
Timing optimization
Timing constraints generation
Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs

Job Summary

  • Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
  • Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
  • Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.

Matching Summary

Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.

Skills & Requirements

Must-have

  • physical design timing analysis
  • timing optimization
  • timing constraints generation
  • timing violation fixes
  • clock network design
  • PVT condition definition

Nice-to-have

  • workload driven leadership
  • collaboration with architecture teams
  • high performance low power design

Key Requirements

  • B.tech/M.tech

Work Rights

Not specified

Tailored Resume

Cover Letter