Sr Asic Design Verification Engineer

Cisco UK

San Jose, US
Base: $165,000.00 - $241,400.00; bonus/equity: not...
Onsite
System verilog and uvm
Asic design and verification processes
Verify blocks/clusters or full chip level
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
  • Participate in the ASIC design verification for Cisco high-end switching products, architecting and developing DV environment infrastructure.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Salary

Base: $165,000.00 - $241,400.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid parental leave, disability, life insurance, stock units, paid time away

Skills & Requirements

Must-have

  • System Verilog and UVM
  • ASIC design and verification processes
  • verify blocks/clusters or full chip level
  • simulation models, test plans, direct and random tests
  • construct testbenches components

Nice-to-have

  • post-silicon lab bring-up experience
  • emulation platforms experience
  • Linux, C/C++, Python/Perl experience
  • collaboration with designers and architects

Key Requirements

  • Bachelor's degree and 7+ years experience
  • Master's degree and 4+ years experience
  • PhD and 1+ year experience
  • Prior experience in System Verilog and UVM
  • Experience with ASIC design and verification processes
  • Experience in verifying blocks/clusters or full chip level

Work Rights

Not specified

Tailored Resume

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