The role involves architecting and designing multi-GPU scale-up and scale-out systems for next-generation datacenter platforms focused on AI and HPC
Job Summary
The role involves architecting and designing multi-GPU scale-up and scale-out systems for next-generation datacenter platforms focused on AI and HPC.
Candidates must collaborate with ASIC, compiler, and software teams to enable efficient hardware-software co-design across compute, memory, and communication layers.
The position requires deep hands-on experience with system-level fabric networking architecture and practical expertise in GPU-to-GPU communication fabrics.
Matching Summary
The role involves architecting and designing multi-GPU scale-up and scale-out systems for next-generation datacenter platforms focused on AI and HPC.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
Multi-GPU system topology architecture
NVLink Ethernet InfiniBand PCIe protocols
RDMA RoCE transport offload architectures
Hardware-software co-design expertise
NUMA memory models and coherency awareness
Nice-to-have
NIC or DPU architecture experience
Chiplet interconnect architecture expertise
2.5D 3D package co-design background
Interposer design experience
Python SystemC modeling skills
Key Requirements
BS/MS/PhD in Electrical or Computer Engineering
8 years or more of relevant system design experience
Deep understanding of NVLink Ethernet InfiniBand CXL and PCIe protocols