Senior Staff Digital Design Engineer – Wireline Phys
Marvell
Base: cad 118,700 - 158,300 py; bonus/equity: not ...
7+ years digital design experience
High-speed phy or serdes development
Rtl design using verilog/systemverilog
This role focuses on delivering next-generation PHY solutions optimized for advanced nodes, low power, and high performance across SerDes and Die-to-Die interfaces
Job Summary
This role focuses on delivering next-generation PHY solutions optimized for advanced nodes, low power, and high performance across SerDes and Die-to-Die interfaces.
Candidates will collaborate with analog teams to define control interfaces and adaptation loops while ensuring robust operation across voltage, temperature, and process corners.
The position offers technical leadership opportunities including mentoring junior engineers and contributing to internal methodology improvements within a cross-disciplinary engineering team.
Matching Summary
This role focuses on delivering next-generation PHY solutions optimized for advanced nodes, low power, and high performance across SerDes and Die-to-Die interfaces.
Salary
Base: CAD 118,700 - 158,300 per annum; Bonus/Equity: Not specified; Benefits: Competitive compensation and great benefits
Skills & Requirements
Must-have
7+ years digital design experience
High-speed PHY or SerDes development
RTL design using Verilog/SystemVerilog
Timing closure and static timing analysis
Clock Domain Crossing (CDC) techniques
Mixed-signal interface collaboration
DFT, BIST, and scan insertion knowledge
Nice-to-have
Python, Perl, or TCL scripting skills
Mentorship of junior engineers
Post-silicon bring-up support
Experience with APB, AHB, AXI protocols
DSP pipeline and calibration logic design
Key Requirements
Master's degree in EE/CE with 7+ years experience
PhD with 4+ years relevant experience
Eligibility for US export control access
Deep knowledge of synthesis and STA
Proficiency with EDA simulation tools
Work Rights
Must be eligible for US export-controlled information