Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies
Job Summary
Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
Provide expert engineering judgment for critical decision-making and complex design trade-offs, including advanced IR drop analysis and mitigation, Reliability Verification (RV) analysis, ECO impact assessment, and project schedule optimization.
Mentor and guide junior layout engineers, providing technical guidance and knowledge transfer.
Matching Summary
Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
Skills & Requirements
Must-have
memory compiler floorplans
cross-functional collaboration
layout implementation assembly
advanced routing techniques
CAD tool utilization
productivity macro development
workflow optimization
IR drop analysis
Reliability Verification analysis
ECO impact assessment
Nice-to-have
technical leadership and mentorship
methodology innovation
process refinement
continuous improvement
strategic planning
cutting-edge memory technologies
Key Requirements
Bachelor's degree in Electronic/Microelectronic Engineering
10+ years custom digital/analog layout design experience
Proficiency in Cadence Virtuoso, Synopsys Custom Compiler