Debugging features like signaltap & system console
Fpga/asic rtl design and verification
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Leads the Partial Reconfiguration (PR) Validation team and creates designs using HDLs and Altera IPs, verifying them for functionality and timing on Altera FPGA Hardware Boards.
Collaborates with cross-functional teams to develop and improve validation strategies for Compiler/PR validation and help resolve customer issues.
Matching Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
Partial Reconfiguration (PR) flow validation
Debugging features like SignalTap & System Console
FPGA/ASIC RTL design and verification
FPGA hardware validation
Shell, Perl/TCL or Python Scripting
Bus protocols like AHB, AXI, PCIe, Ethernet, Avalon
Nice-to-have
Compiler optimizations research
Cross-functional team collaboration
Customer issue resolution
Key Requirements
6+ years of relevant experience
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design
Experience with FPGA Devices like Agilex, Virtex
Experience with Tools like Altera Quartus, Xilinx Vivado, Synplify
Experience with Simulation/Verification tools like VCS, Questa, XCelium, STA