Soc Physical Design Static Timing Analysis Engineer

Intel Retiree Medical Plan Trust

Phoenix, Arizona, United States
Base: $164,470.00-311,890.00 usd; bonus/equity: st...
Hybrid
Soc level static timing analysis
Clock network design experience
Timing closure methodologies
This role plays a pivotal part in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip designs

Job Summary

  • This role plays a pivotal part in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip designs.
  • Candidates will be responsible for generating timing constraints, addressing violations, and developing optimized clock networks for global impact products.
  • The position offers a competitive compensation package including stock bonuses, health benefits, retirement plans, and a hybrid work model.

Matching Summary

This role plays a pivotal part in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip designs.

Salary

Base: $164,470.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation programs

Skills & Requirements

Must-have

  • SOC level static timing analysis
  • Clock network design experience
  • Timing closure methodologies
  • Physical design knowledge
  • TCL scripting proficiency

Nice-to-have

  • DFT architecture knowledge
  • Collaboration across diverse teams
  • Innovative solution development
  • Strong communication skills
  • High-performance physical design flows

Key Requirements

  • Bachelor's degree with 8+ years experience
  • Master's degree with 6+ years experience
  • PhD with 4+ years experience
  • 7+ years technical proficiency in SOC timing
  • 3+ years expertise in timing constraint adaptation

Work Rights

Not specified

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