Senior Analog Validation/characterization Engineer

NXP USA INC.

California, US
Base: $166,200 to $228,500 annually; bonus/equity:...
Mixed-signal engineer experience
Systemverilog or verilog-a modeling
Cadence virtuoso and spectre simulation
This role bridges the gap between pre-silicon design and post-silicon reality by combining behavioral modeling with hands-on hardware validation

Job Summary

  • This role bridges the gap between pre-silicon design and post-silicon reality by combining behavioral modeling with hands-on hardware validation.
  • Candidates will spend roughly half their time developing SystemVerilog or Verilog-A models and the other half characterizing high-speed transceiver silicon in the lab.
  • The position offers a competitive base salary range of $166,200 to $228,500 annually along with health, dental, vision insurance, and 401(k) benefits.

Matching Summary

This role bridges the gap between pre-silicon design and post-silicon reality by combining behavioral modeling with hands-on hardware validation.

Salary

Base: $166,200 to $228,500 annually; Bonus/Equity: Competitive incentive compensation and/or equity available; Benefits: Health, dental, vision, 401(k), paid leave

Skills & Requirements

Must-have

  • Mixed-Signal Engineer experience
  • SystemVerilog or Verilog-A modeling
  • Cadence Virtuoso and Spectre simulation
  • High-speed lab equipment operation
  • Python scripting for automation

Nice-to-have

  • Familiarity with SerDes standards
  • Experience with structured PDP process
  • Knowledge of signal integrity concepts
  • NumPy and Matplotlib library usage

Key Requirements

  • BSEE or MSEE degree required
  • 3+ years of IC modeling or validation experience
  • Strong proficiency in Python scripting

Work Rights

Not specified

Tailored Resume

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