Software Engineer Ii - Verification Using Sv/uvm - Ahmedabad
BETA CAE Systems International AG
Ahmedabad, India
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2 to 4 years domain experience
Proficiency in functional verification using sv/uvm
Strong debugging skills
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BETA CAE Systems International AG is seeking a Software Engineer II for their Ahmedabad location, focusing on verification using SystemVerilog/Universal Verification Methodology (SV/UVM). The ideal candidate will have 2 to 4 years of experience in functional verification, strong programming skills, and a collaborative mindset within a supportive work culture.
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Job Summary
The candidate will develop verification environments and implement test features for Verification IP tools.
Cadence offers a supportive culture focused on employee well-being, career development, and the 'One Cadence – One Team' philosophy.
This role requires strong written, verbal, and presentation skills to collaborate effectively across functions and geographies.
Matching Summary
Match Score: 75
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BETA CAE Systems International AG is seeking a Software Engineer II for their Ahmedabad location, focusing on verification using SystemVerilog/Universal Verification Methodology (SV/UVM). The ideal candidate will have 2 to 4 years of experience in functional verification, strong programming skills, and a collaborative mindset within a supportive work culture.
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Skills & Requirements
Must-have
2 to 4 years domain experience
Proficiency in functional verification using SV/UVM
Strong debugging skills
Hands-on knowledge of C/C++/Scripting
Strong Digital Electronics fundamentals
Nice-to-have
Working experience on MIPI UFS stack
Experience with Unipro and MPHY protocols
Excellent communication skills
Ability to ramp up on new technologies quickly
Self-motivated analytical mindset
Key Requirements
BE/BTech/ME/MS/MTech in Electrical/Electronic
2 to 4 years of domain experience
Strong Digital Electronics and Programming fundamentals