Not specified (considering likely hybrid or flexible arrangements based on company culture).
13-17 years digital functional verification experience
Uvm testbench architecture development
Pcie transaction layer domain expertise
Boeing India is seeking a Senior ASIC-FPGA Verification Engineer with extensive experience in digital functional verification for both ASIC and FPGA products. The ideal candidate will have a strong technical background, particularly in verification methodologies and protocols such as PCIe and Ethernet
Job Summary
Boeing India Engineering seeks a Senior ASIC-FPGA Verification Engineer to support commercial and defense electronics product lines.
The role requires leading verification activities across multiple milestones while developing reusable components like scoreboards and checkers using UVM.
Candidates must drive technical reviews with cross-functional teams and lead AI initiatives for verification automation within the global aerospace sector.
Matching Summary
Match Score: 85
Boeing India is seeking a Senior ASIC-FPGA Verification Engineer with extensive experience in digital functional verification for both ASIC and FPGA products. The ideal candidate will have a strong technical background, particularly in verification methodologies and protocols such as PCIe and Ethernet.
Skills & Requirements
Must-have
13-17 years digital functional verification experience
UVM testbench architecture development
PCIe Transaction layer domain expertise
Ethernet Mac Layer domain expertise
SystemVerilog object-oriented programming
Multiple ASIC FPGA tape out ownership
Mentoring verification engineers
Nice-to-have
AI initiatives for verification automation
Avionics protocols knowledge
DO-254 compliance experience
Power aware simulation debug skills
Gate level simulation debug experience
Linux/Unix terminal command proficiency
Scripting languages Perl Python Shell
Key Requirements
Bachelor degree in Engineering or related field
13 to 17 years of Digital Functional verification experience
8+ years leading verification for multiple tape outs