The role requires leading the definition and implementation of high-speed digital designs for next-generation IO in cutting-edge technology nodes
Job Summary
The role requires leading the definition and implementation of high-speed digital designs for next-generation IO in cutting-edge technology nodes.
Candidates must possess a minimum of 10 years of ASIC frontend experience with strong proficiency in RTL coding and verification environments.
The position involves close collaboration with verification and back-end teams to ensure successful floor planning, physical implementation, and timing closure.
Matching Summary
The role requires leading the definition and implementation of high-speed digital designs for next-generation IO in cutting-edge technology nodes.
Skills & Requirements
Must-have
10 years ASIC frontend experience
RTL coding using HDL languages
High speed digital design implementation
Synthesis STA timing closure
Post Silicon debug support
Nice-to-have
Strong communication and leadership skills
Scripting knowledge desirable
Problem solving and analytical skills
Key Requirements
BS/MS or PhD in Electronics Engineering
Minimum 10 years of ASIC frontend experience
Proficiency with Spyglass, Synthesis, and STA tools