Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level
Job Summary
Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level.
Verify test patterns using gate-level simulations and collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.
At Arrow, we offer competitive financial compensation, including various compensation plans and a solid benefits package, medical, dental, vision insurance, 401k with matching contributions, and paid time off.
Matching Summary
Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level.
Skills & Requirements
Must-have
Scan, MBIST, ATPG, JTAG
DFT specifications and architectures
Debugging DFT issues
Siemens-Tessent, Synopsys for DFT
Silicon debug and data analysis
TCL scripting for automation
Nice-to-have
Collaborate closely with teams
Work in partnership with test engineers
Growth Opportunities
Key Requirements
Proven experience in developing DFT specifications
Proficiency in Siemens-Tessent, Synopsys
Ability to conduct experiments during silicon debug