The job posting is for a Physical Design Lead (Integration QA) at Inteelabs in Penang, Malaysia, focused on overseeing foundational IP integration QA and improving QA processes in semiconductor design. The role requires extensive experience in SoC, analog, IP, or ASIC design, along with strong technical skills in physical design flows and automation
Job Summary
The Foundational IP Integration QA Lead will be a part of FIP Platform and QA team and will oversee the FIP integration QA progress across all nodes.
The team will continuously improve our QA coverage by identifying QA gaps and work on improvement to get these filled.
Work on Full Chip Reference Design Development as the Timing Owner.
Matching Summary
Match Score: 85
The job posting is for a Physical Design Lead (Integration QA) at Inteelabs in Penang, Malaysia, focused on overseeing foundational IP integration QA and improving QA processes in semiconductor design. The role requires extensive experience in SoC, analog, IP, or ASIC design, along with strong technical skills in physical design flows and automation.
Skills & Requirements
Must-have
Physical design flows
Timing convergence
DRC fixes
Reliability verification processes
Static timing analysis
Nice-to-have
Advanced process nodes
Team-oriented environment
High degree of ambiguity
Design productivity and efficiency
Key Requirements
Bachelor of Science degree with 8 years of experience