Asic Engineering Technical Leader

Cisco UK

San Jose, California, USA
Base: $183,800.00 - $303,100.00 (nyc metro); bonus...
Onsite
Verilog/system verilog programming
Interactive and waveform debug
Resolve setup and hold timing violations
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks

Job Summary

  • Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
  • Participate in and contribute to chip architecture definition and discussions, author design specifications, and implement Verilog RTL.
  • Cisco offers a unique experience combining large organization resources with a startup culture, providing opportunities for growth and impact.

Matching Summary

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.

Salary

Base: $183,800.00 - $303,100.00 (NYC Metro); Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k), paid parental leave, disability, life insurance, stock units, paid time off

Skills & Requirements

Must-have

  • Verilog/System Verilog programming
  • Interactive and waveform debug
  • Resolve setup and hold timing violations
  • Micro-architecture solutions development
  • RTL implementation
  • Collaborate with verification team
  • Collaborate with physical design team

Nice-to-have

  • Digital design principles
  • Clock Domain Crossing (CDC)
  • Spyglass static analysis
  • Scripting experience (Python, Perl, TCL)

Key Requirements

  • 10+ years ASIC Design experience (Bachelor's)
  • 8+ years ASIC Design experience (Master's)

Work Rights

Not specified

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