Senior Analog Layout Engineer

NXP Semiconductors

Malaysia
Custom analog layout execution
Advanced nodes layout
Drc, lvs, erc checks
Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators in advanced nodes

Job Summary

  • Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators in advanced nodes.
  • Run and debug DRC, LVS, ERC, and reliability checks, collaborating with designers to close issues and support PEX extraction.
  • Partner closely with analog circuit designers, CAD, and methodology teams, and support silicon bring-up, debug, and yield improvement.

Matching Summary

Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators in advanced nodes.

Skills & Requirements

Must-have

  • Custom analog layout execution
  • Advanced nodes layout
  • DRC, LVS, ERC checks
  • Cadence Virtuoso Layout Suite
  • Calibre tool proficiency

Nice-to-have

  • Automotive product experience
  • Low-noise, high-speed analog
  • Mentor junior engineers
  • ISO / automotive quality flows

Key Requirements

  • 6-10 years hands-on experience
  • 28nm, 22nm, 16nm CMOS experience
  • BSEE or equivalent degree

Work Rights

Not specified

Tailored Resume

Cover Letter