Analog Circuit Design Engineer

Intel Retiree Medical Plan Trust

Hillsboro, Oregon, US
Base: $141,910.00-269,100.00 usd annually; bonus/e...
**
Analog/rf circuit design experience
Cadence virtuoso layout generation
Spice level simulation expertise
** The Analog Circuit Design Engineer position at Intel Retiree Medical Plan Trust involves designing foundational collateral for Intel's CPU and SoC products. The ideal candidate should have a background in analog/RF circuit design, experience with SPICE level circuit simulation, and proficiency in data analysis/scripting. The role offers a competitive compensation package and the flexibility of a hybrid work model. **

Job Summary

  • The role involves designing critical foundational collateral on leading edge Intel processes to meet density and performance scaling goals.
  • Candidates will collaborate with process/device, PDK/modeling, and product teams to co-optimize design and technology through test chips.
  • The position offers a competitive compensation package including stock bonuses and comprehensive health and retirement benefits.

Matching Summary

Match Score: 75

** The Analog Circuit Design Engineer position at Intel Retiree Medical Plan Trust involves designing foundational collateral for Intel's CPU and SoC products. The ideal candidate should have a background in analog/RF circuit design, experience with SPICE level circuit simulation, and proficiency in data analysis/scripting. The role offers a competitive compensation package and the flexibility of a hybrid work model. **

Salary

Base: $141,910.00-269,100.00 USD annually; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • Analog/RF circuit design experience
  • Cadence Virtuoso layout generation
  • SPICE level simulation expertise
  • Python or Matlab data analysis scripting

Nice-to-have

  • Device physics fundamentals knowledge
  • EM/IR reliability check experience
  • Pcell design using SKILL language
  • Machine learning for design space exploration
  • Post silicon characterization and debug

Key Requirements

  • Bachelor's degree in EE with 4+ years experience
  • Master's degree in EE with 3+ years experience
  • Ph.D. in EE with 6+ months professional experience
  • 3+ years SPICE simulation and Cadence Virtuoso usage
  • 3+ years data analysis scripting experience

Work Rights

Not specified

Tailored Resume

Cover Letter