Fpga Digital Design And Verification Engineer-contract
Indclutch
San Jose, California, United States
Base: $100-105k usd; bonus/equity: not specified; ...
On-site
Systemverilog/uvm verification environments
Risc-v design
Digital design methodologies
This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments
Job Summary
This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
We use artificial intelligence to screen, assess, or select applicants for the position.
Matching Summary
This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments.
Salary
Base: $100-105K USD; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
SystemVerilog/UVM verification environments
RISC-V design
digital design methodologies
RTL block verification
communication protocols verification
Nice-to-have
AI/ML accelerators
SoC components verification
FPGA tools experience
Key Requirements
Bachelor’s Degree in Computer or Electrical Engineering
1+ years' experience in Digital Logic Design
RISC-V and digital design experience
Proficiency in SystemVerilog and Verilog
Knowledge of UVM, functional coverage, constrained random verification, and assertions
Experience using simulation and verification tools
Familiarity with Linux-based development environments
Ability to debug simulation issues and analyze waveforms