Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements
Job Summary
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Matching Summary
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Skills & Requirements
Must-have
Verilog/System Verilog IP verification
mixed signal logic components
develops IP verification plans
executes verification plans
root causes and debugs issues
collaborates with design teams
Nice-to-have
UVM coding
low-power design using UPF
multiple clock domain design
state machine design
checker development
subsystem to SoC integration
coding coverage and assertions
mixed signal verification
GLS verification
Key Requirements
BE/B.Tech with 12 years experience OR ME/M.Tech with 10 years experience