Senior Physical Design Application Engineer

Intel Corporation

Phoenix, Arizona, United States
Base: $122,440.00-232,190.00 usd; bonus/equity: st...
Hybrid
4+ years experience with advanced cmos processes
3+ years asic physical design implementation
Cadence tool suite proficiency

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 4+ years experience with advanced CMOS processes
  • 3+ years ASIC physical design implementation
  • Cadence tool suite proficiency
  • Python Perl Tcl shell scripting skills
  • US Citizenship required

Nice-to-have

  • Active US Government Security Clearance
  • Customer-facing technical support experience
  • Experience with 7nm process technology
  • Synopsys tools knowledge
  • Hierarchical multi-voltage domain design

Key Requirements

  • Bachelor's degree in Electrical Engineering or STEM field
  • US Citizenship mandatory
  • Ability to obtain US Government Security Clearance
  • 4+ years experience with 22nm and below processes
  • 3+ years in ASIC physical design and signoff

Work Rights

Must have US citizenship

Tailored Resume

Cover Letter