Senior Emulation Engineer

Inteelabs

Phoenix, Arizona, US
Base: $122,440.00-232,190.00 usd; bonus/equity: st...
Hybrid
Fpga and emulation
Rtl coding
Hybrid fpga emulation models
Develop and enable Accelerator IPs in Intel platforms by implementing and debugging complex hybrid models of SOCs, chiplet dies and the IP's for pre and post Silicon Validation and debug purposes

Job Summary

  • Develop and enable Accelerator IPs in Intel platforms by implementing and debugging complex hybrid models of SOCs, chiplet dies and the IP's for pre and post Silicon Validation and debug purposes.
  • Define and develop new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Develop and enable Accelerator IPs in Intel platforms by implementing and debugging complex hybrid models of SOCs, chiplet dies and the IP's for pre and post Silicon Validation and debug purposes.

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • FPGA and Emulation
  • RTL coding
  • Hybrid FPGA emulation models
  • FPGA synthesis, partitioning and routing tools
  • HW/SW tools for acceleration
  • FPGA emulation model testing and debug

Nice-to-have

  • Linux admin or end user experience
  • Wireless and Networking Protocols knowledge
  • PCIE knowledge
  • Scripting languages (TCL, Perl)

Key Requirements

  • Bachelor's and 6+ years or Master's and 5+ years experience
  • 4+ years in RTL coding
  • 4+ years in lab environment and debug skills
  • 4+ years in FPGAs and Emulation

Work Rights

Not specified

Tailored Resume

Cover Letter