Ai enabled dv development including rootcause analysis
Analog Devices is seeking a Staff Engineer in Design Verification Engineering to join their expanding team focused on Foundational Security Solutions. The ideal candidate will have extensive experience in digital verification, particularly in System Verilog and UVM, and will be responsible for developing test benches and methodologies while mentoring junior engineers
Job Summary
Analog Devices is expanding its team to architect, design, and verify Foundational Security Solutions for internal and external customers.
The role involves developing UVM test benches to verify blocks, subsystems, and SOC level IP while achieving high coverage against specifications.
Candidates will lead and mentor the local DV team while proactively communicating status to management using Agile development practices.
Matching Summary
Match Score: 85
Analog Devices is seeking a Staff Engineer in Design Verification Engineering to join their expanding team focused on Foundational Security Solutions. The ideal candidate will have extensive experience in digital verification, particularly in System Verilog and UVM, and will be responsible for developing test benches and methodologies while mentoring junior engineers.
Skills & Requirements
Must-have
7+ years digital verification experience
Expert-level System Verilog and UVM knowledge
AI enabled DV development including rootcause analysis
Experience with Legacy and Post Quantum crypto accelerators
Portable testing across block subsystem and chip levels
Nice-to-have
Python SystemC C/C++ programming skills
FPGA HW emulation SystemC platform experience
Leading DV teams embedded in cross-functional groups
Reuse mindset and demonstrated experience
Agile development practices communication skills
Key Requirements
BSEE/MSEE degree required
7+ years of digital verification experience
US Citizenship or Permanent Resident status required for export control
Work Rights
Must be US Citizen, US Permanent Resident, or protected individual