Physical Design Engineer (pnr/physical Verification/sta/emir)

Cadence

Hybrid
Physical design implementation experience
Advanced technology node knowledge n7/n5
Static timing analysis expertise
Cadence is seeking a Physical Design Engineer to work on challenging designs, focusing on next-generation PHY IP physical design and methodology. The ideal candidate should have extensive experience in physical design implementation and a strong background in static timing analysis

Job Summary

  • The candidate will work on challenging low power and high speed designs while participating in next-generation physical design methodology development.
  • Responsibilities include performing comprehensive physical design tasks such as floor planning, power grid design, place and route, and timing closure.
  • Candidates must possess extensive knowledge of design rules for advanced process nodes like N7 and N5 or below.

Matching Summary

Match Score: 85

Cadence is seeking a Physical Design Engineer to work on challenging designs, focusing on next-generation PHY IP physical design and methodology. The ideal candidate should have extensive experience in physical design implementation and a strong background in static timing analysis.

Skills & Requirements

Must-have

  • Physical design implementation experience
  • Advanced technology node knowledge N7/N5
  • Static timing analysis expertise
  • DRC DFM LVS antenna violation fixing
  • Scripting languages for methodology

Nice-to-have

  • Leadership in flow development
  • Collaboration with RTL and Analog teams
  • Quick learning ability
  • High level communication skills
  • Persistence and responsibility

Key Requirements

  • Bachelor degree in EE CS IT
  • 5+ years work experience
  • Deep experience in static timing analysis

Work Rights

Not specified

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