Mixed Signal Logic Verification Engineer

Intel Corporation

Bangalore, India
Hybrid
System verilog and uvm
Mix signal ip verification strategy
Rtl debug and gate-level simulations
Drive complex SoC/ASIC verification with a focus on UVM/System Verilog testbench architecture and Mix signal IP verification strategy

Job Summary

  • Drive complex SoC/ASIC verification with a focus on UVM/System Verilog testbench architecture and Mix signal IP verification strategy.
  • Develop, implement, and lead comprehensive verification plans, mentor junior engineers, and improve verification methodologies.
  • Collaborate with architects and design teams to resolve issues, including post-silicon failures, and ensure coverage closure.

Matching Summary

Drive complex SoC/ASIC verification with a focus on UVM/System Verilog testbench architecture and Mix signal IP verification strategy.

Skills & Requirements

Must-have

  • System Verilog and UVM
  • Mix signal IP verification strategy
  • RTL debug and gate-level simulations
  • Constraint-random test generation
  • Python, Perl, Tcl scripting

Nice-to-have

  • Formal verification methods
  • Mentoring junior engineers
  • Post-silicon debug experience

Key Requirements

  • 11-15 years of ASIC/SoC verification experience
  • Expert-level System Verilog, UVM, Verilog
  • Proficiency in JTAG/IJTAG/CRI/APB protocols
  • Experience with Synopsys VCS, Cadence Xcelium/JasperGold
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering

Work Rights

Not specified

Tailored Resume

Cover Letter