SpaceX is seeking a Senior Engineer to develop cutting-edge next-generation silicon for Starlink satellites and ground infrastructure
Job Summary
SpaceX is seeking a Senior Engineer to develop cutting-edge next-generation silicon for Starlink satellites and ground infrastructure.
The role involves performing partition synthesis, floorplanning, place and route, and resolving timing and congestion issues using industry standard EDA tools.
Candidates must be willing to work extended hours and weekends as needed to meet critical project milestones.
Matching Summary
SpaceX is seeking a Senior Engineer to develop cutting-edge next-generation silicon for Starlink satellites and ground infrastructure.
Salary
Base: $160,000.00 - $220,000.00 per year; Bonus/Equity: Eligible for stock options and long-term incentives; Benefits: Medical, dental, vision, 401(k), paid leave
Skills & Requirements
Must-have
5+ years ASIC physical design experience
RTL2GDSII physical design and signoff flows
STA noise logic equivalency verification
Deep sub-micron FinFET and CMOS physics knowledge
Nice-to-have
Strong scripting skills in Python TCL Perl
Experience with DFT Scan MBIST LBIST
Self-driven attitude in dynamic group environment
Understanding of CMOS analog circuit design
Key Requirements
Bachelor's degree in electrical engineering or computer science
U.S. citizenship or lawful permanent resident status required
Ability to work extended hours and weekends
Work Rights
Must have US citizenship, green card, refugee, or asylee status