Staff Engineer, Dft

Marvell Technology

**
Scan insertion and atpg tools
Mbist/occ validation flows
Hierarchical dft and sdc
** Marvell Technology is seeking a Staff Engineer for their DFT (Design for Test) team, focusing on the development and integration of advanced testing methodologies for complex ASIC/SoC designs. The ideal candidate should possess strong expertise in DFT tools and methodologies, along with solid experience in digital circuit design, and will work collaboratively with cross-functional teams. **

Job Summary

  • Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
  • You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses.
  • With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.

Matching Summary

Match Score: 75

** Marvell Technology is seeking a Staff Engineer for their DFT (Design for Test) team, focusing on the development and integration of advanced testing methodologies for complex ASIC/SoC designs. The ideal candidate should possess strong expertise in DFT tools and methodologies, along with solid experience in digital circuit design, and will work collaboratively with cross-functional teams. **

Skills & Requirements

Must-have

  • Scan insertion and ATPG tools
  • MBIST/OCC validation flows
  • Hierarchical DFT and SDC
  • SpyGlass DFT checks
  • Pre-silicon validation and post-silicon bring-up
  • Scripting for automation

Nice-to-have

  • Collaborate with RTL, synthesis, and physical design
  • Optimize test methodologies for cost, coverage, and yield
  • Cross-functional collaboration skills

Key Requirements

  • 5 to 8 years of experience in DFT
  • Bachelor’s/Master’s degree in Electrical/Electronics Engineering, VLSI, or related field
  • Solid understanding of SSN design and IEEE 1687 IJTAG
  • Good understanding of RTL design, synthesis, STA, and physical design flows
  • Hands-on experience with silicon bring-up and debug
  • Eligible to access export-controlled information

Work Rights

Not specified

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