Junior Layout Engineer

NXP USA INC.

Catania, Italy
0-2 years analog layout experience
Cadence virtuoso oa pvs expertise
Mentor graphics calibre drc lvs
This role involves delivering floorplan activities and analog layout blocks for high-performance microcontrollers in a fast-paced consumer environment

Job Summary

  • This role involves delivering floorplan activities and analog layout blocks for high-performance microcontrollers in a fast-paced consumer environment.
  • Candidates will run physical verifications including DRC, LVS, DFM, and parasitic extractions to ensure zero-defect product delivery.
  • The team supports MCU and analog custom products designed globally with a strong focus on design for quality and long-term reliability.

Matching Summary

This role involves delivering floorplan activities and analog layout blocks for high-performance microcontrollers in a fast-paced consumer environment.

Skills & Requirements

Must-have

  • 0-2 years Analog layout experience
  • Cadence Virtuoso OA PVS expertise
  • Mentor Graphics Calibre DRC LVS
  • Device physics and ESD protection knowledge
  • Floorplan activities at IP level

Nice-to-have

  • Cross-functional collaboration skills
  • Technical training and guideline writing
  • Global environment communication ability
  • Design for quality focus

Key Requirements

  • MSEE or BSEE degree required
  • 0-2 years leading Analog layout activities
  • Experience with complex ICs

Work Rights

Not specified

Tailored Resume

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