Design Verification Engineer (SoC/ASIC/RTL)

HKM HR MANAGEMENT PTE. LTD.

Singapore, Singapore
Uvm/ovm verification methodology
Systemverilog and verilog coding
Constrained-random test development
The role involves creating detailed test plans and managing infrastructure for automated SoC verification alongside design engineers

Job Summary

  • The role involves creating detailed test plans and managing infrastructure for automated SoC verification alongside design engineers.
  • Candidates must develop reusable testbenches and regression strategies to ensure comprehensive function coverage before tape-out.
  • The position requires mentoring team members and providing post-silicon validation support to enhance overall verification efficiency.

Matching Summary

Match Score: 75

The role involves creating detailed test plans and managing infrastructure for automated SoC verification alongside design engineers.

Skills & Requirements

Must-have

  • UVM/OVM verification methodology
  • SystemVerilog and Verilog coding
  • Constrained-random test development
  • Regression strategy creation
  • AMBA bus protocol knowledge
  • Hardware-software co-verification

Nice-to-have

  • Mentoring junior engineers
  • Post-silicon validation support
  • RISC-V or ARM core experience
  • DSP core verification background
  • Scripting in Python and Perl

Key Requirements

  • Master's degree in Electrical Engineering with 8 years experience
  • PhD in Electrical Engineering with 3 years experience
  • Experience verifying designs at RTL and post-P&R gate levels

Work Rights

Not specified

Tailored Resume

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