Senior Asic Design Verification Engineer

Hewlett Packard Enterprise

Not specified; not specified; comprehensive suite ...
Onsite
15+ years asic verification experience
Systemverilog and uvm methodology expertise
Vcs or nc-sim simulation tool proficiency
Hewlett Packard Enterprise is seeking a Senior ASIC Design Verification Engineer to work onsite, primarily focusing on advanced verification of complex ASIC features using UVM methodology. The role requires extensive experience in ASIC verification, strong technical skills, and a collaborative mindset

Job Summary

  • This role involves driving advanced verification using UVM methodology to validate complex ASIC features at Hewlett Packard Enterprise.
  • Candidates will own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off.
  • The company offers comprehensive health benefits and invests in personal and professional development for its team members.

Matching Summary

Match Score: 85

Hewlett Packard Enterprise is seeking a Senior ASIC Design Verification Engineer to work onsite, primarily focusing on advanced verification of complex ASIC features using UVM methodology. The role requires extensive experience in ASIC verification, strong technical skills, and a collaborative mindset.

Salary

Not specified; Not specified; Comprehensive suite of benefits provided

Skills & Requirements

Must-have

  • 15+ years ASIC verification experience
  • SystemVerilog and UVM methodology expertise
  • VCS or NC-Sim simulation tool proficiency

Nice-to-have

  • Python scripting skills
  • Networking protocol exposure like Ethernet
  • Technical leadership mindset

Key Requirements

  • B.E/B.Tech or M.E/M.Tech in Electronics
  • 15+ years of ASIC verification experience
  • Strong SystemVerilog and UVM skills

Work Rights

Not specified

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