The role involves logic design of component and foundation IPs which can be used to build an SoC chassis
Job Summary
The role involves logic design of component and foundation IPs which can be used to build an SoC chassis.
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Matching Summary
The role involves logic design of component and foundation IPs which can be used to build an SoC chassis.
Skills & Requirements
Must-have
Verilog/System Verilog skills
logic design of IPs
protocol conversion bridges
AMBA/CXL protocols
PPA trade-offs understanding
Nice-to-have
QoS, access control, flow control
debug, RAS, security, error handling
AI to assist logic design
Key Requirements
4+ years of experience
Bachelor's/Master's degree in Science, Electrical Engineering or equivalent
Verilog/System Verilog, Lint/CDC/RDC
AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols
working with architecture, verification SoC integration teams