Digital Asic Prototyping Engineer

Ciena Corporation

Base: $109,000 - $174,000 annually; bonus/equity: ...
Not specified
Digital design synthesis and sta experience
Proficiency with system verilog for design
Fpga implementation and timing closure skills
Ciena Corporation is seeking a Digital ASIC Prototyping Engineer to join their team, focusing on the design and verification of WaveLogic ASICs. The ideal candidate will have a background in electrical or computer engineering, experience with FPGA tools, and strong problem-solving abilities

Job Summary

  • This role involves adapting strategic portions of WaveLogic ASICs onto various FPGA prototyping platforms to improve verification processes.
  • The successful candidate will be accountable for creating and integrating ASIC RTL source code, algorithms, and functions targeting FPGAs.
  • Ciena offers a comprehensive benefits package including medical, dental, vision plans, 401(K) matching, and an Employee Stock Purchase Program.

Matching Summary

Match Score: 85

Ciena Corporation is seeking a Digital ASIC Prototyping Engineer to join their team, focusing on the design and verification of WaveLogic ASICs. The ideal candidate will have a background in electrical or computer engineering, experience with FPGA tools, and strong problem-solving abilities.

Salary

Base: $109,000 - $174,000 annually; Bonus/Equity: Discretionary incentive bonus eligible for non-sales employees; Benefits: Medical, dental, vision, 401(K), ESPP, paid leave

Skills & Requirements

Must-have

  • Digital design synthesis and STA experience
  • Proficiency with System Verilog for design
  • FPGA implementation and timing closure skills
  • Understanding of asynchronous clock domain crossing
  • Experience with major FPGA vendor tools

Nice-to-have

  • Self-starter with strong organizational skills
  • Excellent written and oral communication abilities
  • Ability to work independently within a team
  • Methodical approach to solving complex problems

Key Requirements

  • Electrical or computer engineering degree (BEng/BSc or MEng/MSc)
  • Proficiency in System Verilog
  • Experience with digital design synthesis and timing closure

Work Rights

Not specified

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