Analog Layout Design Summer 2026 Intern

Cadence

CARY, NC, USA
Not specified (assumed to be onsite due to the nature of the internship).
Pursuing bsee or msee degree
Understanding layout effects on circuit performance
Knowledge of analog layout techniques like matching
Cadence is seeking an Analog Layout Design Summer 2026 Intern to join their custom layout team in Cary, NC. The role involves developing high-quality CMOS integrated circuits, working collaboratively with experienced designers and engineers, and utilizing industry-leading tools

Job Summary

  • The role involves implementing high-speed and high-accuracy cells, blocks, and IP blocks for advanced CMOS nodes.
  • Interns will collaborate with seasoned custom layout designers and experienced circuit designers globally to meet technical needs.
  • Candidates will have the opportunity to work with Cadence R&D teams to develop and validate Virtuoso and Pegasus tool improvements.

Matching Summary

Match Score: 85

Cadence is seeking an Analog Layout Design Summer 2026 Intern to join their custom layout team in Cary, NC. The role involves developing high-quality CMOS integrated circuits, working collaboratively with experienced designers and engineers, and utilizing industry-leading tools.

Skills & Requirements

Must-have

  • Pursuing BSEE or MSEE degree
  • Understanding layout effects on circuit performance
  • Knowledge of analog layout techniques like matching

Nice-to-have

  • Exposure to Cadence Virtuoso Layout tools
  • Experience with physical verification tools
  • Team player with excellent communication skills

Key Requirements

  • Currently pursuing BSEE or MSEE degree
  • Exposure to microelectronics design requirements

Work Rights

Not specified

Tailored Resume

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