Asic Engineering Technical Leader- Dft

Cisco UK

San Jose, California, United States
Base: $210,600.00 - $305,100.00; bonus/equity: eli...
10 years of asic experience
Post-silicon debug expertise
Jtag protocols and scan architecture
You will serve as an ASIC Technical Lead in the Silicon One development organization focusing on Design-for-Test strategies

Job Summary

  • You will serve as an ASIC Technical Lead in the Silicon One development organization focusing on Design-for-Test strategies.
  • The role involves driving DFT requirements early in the design cycle and leading the quality process through implementation and post-silicon validation.
  • Cisco offers a competitive salary range up to $350,800 depending on location, along with comprehensive benefits including equity and flexible vacation time.

Matching Summary

You will serve as an ASIC Technical Lead in the Silicon One development organization focusing on Design-for-Test strategies.

Salary

Base: $210,600.00 - $305,100.00; Bonus/Equity: Eligible for restricted stock units and annual bonuses; Benefits: Medical, dental, vision, 401(k), paid parental leave, and flexible vacation

Skills & Requirements

Must-have

  • 10 years of ASIC experience
  • Post-silicon debug expertise
  • Jtag protocols and Scan architecture
  • BIST architectures including memory BIST
  • ATPG and EDA tools proficiency
  • Gate level simulation debugging

Nice-to-have

  • Verilog design for custom DFT logic
  • Functional verification skills
  • Test CAD development experience
  • Static Timing Analysis knowledge
  • System Verilog Logic Equivalency checking

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • Minimum 10 years of relevant industry experience
  • Prior experience with TestMax, Tetramax, Tessent, and PrimeTime tools
  • Experience with VCS simulator for gate level simulation

Work Rights

Not specified

Tailored Resume

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