Lead Design Engineer

Cadence

Bangalore, India
6-10 years rtl integration experience
Verilog proficiency required
System verilog and uvm environment usage
The role focuses on integrating, verifying, and releasing IP solutions for Cadence customers in Bangalore

Job Summary

  • The role focuses on integrating, verifying, and releasing IP solutions for Cadence customers in Bangalore.
  • Candidates must possess deep expertise in ASIC development flows including Lint, CDC, Synthesis, and STA.
  • Proficiency in debugging complex protocols and ensuring clean designs for various customer configurations is essential.

Matching Summary

The role focuses on integrating, verifying, and releasing IP solutions for Cadence customers in Bangalore.

Skills & Requirements

Must-have

  • 6-10 years RTL integration experience
  • Verilog proficiency required
  • System Verilog and UVM environment usage
  • Complex protocol implementation experience
  • LINT and CDC design guideline compliance

Nice-to-have

  • PCIe/CXL/IDE protocol experience
  • Genus synthesis tool knowledge
  • Scripting language capabilities
  • Prior IP development team background
  • Debugging and flow setup skills

Key Requirements

  • BE/BTech/ME/MTech in Electrical/Electronics/VLSI
  • 6-10 years core RTL integration and verification experience
  • Experience with System Verilog and UVM based environments

Work Rights

Not specified

Tailored Resume

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