Soc Architect, Coherent Interconnect

Samsung

Austin, Texas, USA
Base: $180,200 - $297,200; bonus/equity: mbo bonus...
Onsite
Coherent interconnect architectures
Cache coherence protocols
Network-on-chip (noc) designs
As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning

Job Summary

  • As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning.
  • You analyze and optimize interconnect performance, power consumption, and area efficiency (PPA) using simulation tools, modeling, and benchmarking to ensure design excellence and achieve competitive advantage in alignment with Samsung's strategic goals and industry trends.
  • The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices.

Matching Summary

As a SoC Architect, you will contribute to the architecture of SoC memory and cache subsystems for Samsung’s premium chipsets, with a strong focus on enabling on-device machine learning.

Salary

Base: $180,200 - $297,200; Bonus/Equity: MBO bonus compensation, long term incentive plan; Benefits: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance, paid time off, student loan program, wellness incentives

Skills & Requirements

Must-have

  • coherent interconnect architectures
  • cache coherence protocols
  • Network-on-chip (NoC) designs
  • high-speed interface protocols
  • system-level design principles

Nice-to-have

  • on-device ML for LLMs
  • Android Ecosystem analysis tools
  • Arm Architecture and ecosystem

Key Requirements

  • 15+ years of experience with a Bachelor’s Degree
  • 13+ years of experience with a Master’s Degree
  • 11+ years of experience with a Ph.D
  • Proficient in cache subsystems
  • Prior experience working on NoC designs
  • Skilled in C, C++, Python, Verilog/VHDL

Work Rights

Requires ability to access export-controlled information

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