Design Verification Engineer, Principal

Marvell

Santa Clara, CA, United States
Base: 158,600 - 237,600; bonus/equity: not specifi...
System verilog expertise
Uvm experience
Verification test plan development
Marvell’s semiconductor solutions are essential building blocks of data infrastructure

Job Summary

  • Marvell’s semiconductor solutions are essential building blocks of data infrastructure.
  • You will verify circuitry in chips for various markets including telecom and automotive.
  • The role includes developing verification environments and leading a team of engineers.

Matching Summary

Marvell’s semiconductor solutions are essential building blocks of data infrastructure.

Salary

Base: 158,600 - 237,600; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • System Verilog expertise
  • UVM experience
  • Verification test plan development

Nice-to-have

  • Detail-oriented and diligent
  • Ability to work with differing opinions
  • Fast-paced learning capability

Key Requirements

  • 10+ years of verification experience
  • Experience with Python or Perl
  • Understanding of networking protocols

Work Rights

Not specified

Tailored Resume

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