Verification Engineer - Cisco Silicon One

Cisco UK

6+ years digital logic design verification experience
Advanced systemverilog knowledge
Uvm methodology expertise
Join the Cisco Silicon One Front-End Design Verification team to validate the most advanced networking silicon in the world

Job Summary

  • Join the Cisco Silicon One Front-End Design Verification team to validate the most advanced networking silicon in the world.
  • Develop advanced verification environments using SystemVerilog and UVM while driving pre-silicon and in-lab debug activities.
  • Collaborate with RTL, architecture, and physical design teams within a startup-like culture backed by Cisco's resources.

Matching Summary

Join the Cisco Silicon One Front-End Design Verification team to validate the most advanced networking silicon in the world.

Skills & Requirements

Must-have

  • 6+ years digital logic design verification experience
  • Advanced SystemVerilog knowledge
  • UVM methodology expertise
  • Pre-silicon and in-lab debug skills

Nice-to-have

  • Python, Perl, TCL, or shell scripting
  • System-level integration experience
  • Driver-level software knowledge
  • CDC concepts familiarity

Key Requirements

  • 6+ years of experience in digital logic design verification
  • Advanced knowledge of SystemVerilog and UVM

Work Rights

Not specified

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