Sr Staff Engineer, Soc Rtl Design

Tenstorrent

Toronto, Canada
On-site
Rtl development (verilog/vhdl)
Asic flows
Power, performance, area (ppa) optimization
Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads

Job Summary

  • Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads.
  • This role involves architecture and RTL implementation of custom IP blocks and SoC components, with performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
  • The company offers a highly competitive compensation package and benefits, and is an equal opportunity employer.

Matching Summary

Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads.

Skills & Requirements

Must-have

  • RTL development (Verilog/VHDL)
  • ASIC flows
  • Power, performance, area (PPA) optimization
  • Architecture and RTL implementation
  • Performance-aware design decisions

Nice-to-have

  • On-chip fabric and interconnect designs
  • Collaboration and technical leadership
  • RISC-V CPU development

Key Requirements

  • Digital design expert
  • Deep understanding of computer architecture
  • IP microarchitecture expertise
  • Full ASIC flows familiarity
  • Synthesis and timing closure awareness
  • Eligibility to access U.S. export-controlled technology

Work Rights

Eligibility to access U.S. export-controlled technology

Tailored Resume

Cover Letter