Senior To Senior Staff, Digital Design Engineer

Marvell

Competitive salary; 13th-month salary + performanc...
Verilog systemverilog rtl implementation
Axi ahb apb on-chip bus protocols
Timing closure coverage analysis
This role involves designing next-generation silicon IP for Marvell's core products used by major tech companies and chip manufacturers

Job Summary

  • This role involves designing next-generation silicon IP for Marvell's core products used by major tech companies and chip manufacturers.
  • Team members participate in the full design lifecycle from architecture discussion and RTL coding to layout and silicon validation.
  • The position offers competitive compensation including a 13th-month salary, performance bonuses, RSUs, and premium health insurance.

Matching Summary

This role involves designing next-generation silicon IP for Marvell's core products used by major tech companies and chip manufacturers.

Salary

Competitive salary; 13th-month salary and performance-based bonus; RSUs included

Skills & Requirements

Must-have

  • Verilog SystemVerilog RTL implementation
  • AXI AHB APB on-chip bus protocols
  • Timing closure coverage analysis
  • UVM based test bench understanding
  • Python Perl TCL scripting skills

Nice-to-have

  • Experience as a technical lead
  • Firmware development support experience
  • Silicon debug and root cause analysis

Key Requirements

  • Minimum BSEE degree required
  • 5 years of digital design experience
  • Eligibility for US export control access

Work Rights

Must be eligible to access export-controlled information under US law

Tailored Resume

Cover Letter