Sr. Dft Engineer

NXP USA INC.

Pune, India
On-site
Dft methodologies: scan, mbist, lbist, jtag
Atpg tools
Upf/cpf-based low-power dft
NXP USA Inc. is seeking a Senior DFT Engineer in Pune, India, responsible for designing and verifying DFT architectures for complex SoCs. The ideal candidate should have extensive expertise in DFT methodologies, hands-on experience with ATPG tools, and a strong background in silicon debug and ATE bring-up

Job Summary

  • You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs.
  • You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.
  • Optimize test coverage, pattern count, and test time.

Matching Summary

Match Score: 85

NXP USA Inc. is seeking a Senior DFT Engineer in Pune, India, responsible for designing and verifying DFT architectures for complex SoCs. The ideal candidate should have extensive expertise in DFT methodologies, hands-on experience with ATPG tools, and a strong background in silicon debug and ATE bring-up.

Skills & Requirements

Must-have

  • DFT methodologies: Scan, MBIST, LBIST, JTAG
  • ATPG tools
  • UPF/CPF-based low-power DFT
  • Fault models (stuck-at, transition, path delay)
  • Physical design constraints for DFT
  • Silicon debug and ATE bring-up

Nice-to-have

  • SoC level DFT experience
  • High-speed interfaces and DFT for mixed-signal blocks
  • Strong problem-solving skills
  • Communication skills

Key Requirements

  • Bachelor’s or Master’s in Electrical/Electronics Engineering
  • Experience in silicon debug and ATE bring-up

Work Rights

Not specified

Tailored Resume

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