Base: $180,200 to $270,400; bonus: mbo bonus compe...
Onsite
10+ years dfx expertise
Dft scan architecture definition
Rtl creation and lint
This role involves defining DFT scan architecture through to pattern generation and silicon debug for bleeding-edge process nodes
Job Summary
This role involves defining DFT scan architecture through to pattern generation and silicon debug for bleeding-edge process nodes.
The position requires balancing test coverage, test time, and execution while collaborating with SOC, Product, and Test Engineering teams.
Samsung offers a competitive base pay range between $180,200 and $270,400 along with comprehensive benefits including medical, dental, vision, and 401(k).
Matching Summary
This role involves defining DFT scan architecture through to pattern generation and silicon debug for bleeding-edge process nodes.
Salary
Base: $180,200 to $270,400; Bonus: MBO bonus compensation based on performance; Benefits: Medical, dental, vision, life insurance, 401(k), free onsite lunch, tuition assistance
Skills & Requirements
Must-have
10+ years DFx expertise
DFT scan architecture definition
RTL creation and LINT
ATPG and simulation
Silicon debug and test escapes
SOC-level interface design
Nice-to-have
Multi-voltage domain implementation
Hierarchical DFT approaches
Streaming fabric exposure
Collaboration with global stakeholders
Creative problem solving skills
Key Requirements
Bachelor's degree plus 10+ years experience
Master's degree plus 8+ years experience
PhD plus 6+ years experience
Multiple tapeouts for digital IP or SOC
US export control eligibility required
Work Rights
Must be eligible to access export-controlled information