Senior Custom Soc Ip Verification Engineer

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Synopsys vcs or cadence xcelium simulator
Verdi, jaspergold or vc formal
Uvm and c++ testbenches
Responsible for ASIC design verification for various IPs at IP and SOC levels

Job Summary

  • Responsible for ASIC design verification for various IPs at IP and SOC levels.
  • Contribute to the innovative verification methodology development, functional and code coverage closure.
  • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing.

Matching Summary

Responsible for ASIC design verification for various IPs at IP and SOC levels.

Skills & Requirements

Must-have

  • Synopsys VCS or Cadence Xcelium Simulator
  • Verdi, JasperGold or VC Formal
  • UVM and C++ testbenches
  • constraint random test
  • coverage-driven verification closure
  • Perl or Python

Nice-to-have

  • passion and desire to deliver innovative products
  • motivated individual
  • complex SOC and IPs
  • various development cycles
  • innovative verification methodology development
  • complex mixed language

Key Requirements

  • 5+ years of experience
  • B.S. or M.S. degree
  • first-pass success in ASIC Development
  • managing and delivering complex mixed language UVM and C++ testbenches
  • interpreting functional specs and creating comprehensive test plans
  • writing directed and constraint random test
  • Strong programming skills in C++/SystemC
  • Familiar with the GDB debugging

Work Rights

Not specified

Tailored Resume

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