Ae - Verification Ip, High-performance Computing (hpc) Protocols

Cadence

San Jose, CA, US
Base: $102,900 to $191,100; bonus/equity: incentiv...
Pcie protocol expertise
Verilog, system verilog, uvm
Debugging pre-silicon verification failures
Bridge the gap between Cadence's R&D and its customers by providing technical expertise for their Verification IP (VIP) portfolio

Job Summary

  • Bridge the gap between Cadence's R&D and its customers by providing technical expertise for their Verification IP (VIP) portfolio.
  • Conduct product demonstrations, manage customer evaluations, and run benchmarks to prove tool value.
  • Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Matching Summary

Bridge the gap between Cadence's R&D and its customers by providing technical expertise for their Verification IP (VIP) portfolio.

Salary

Base: $102,900 to $191,100; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k), ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • PCIe protocol expertise
  • Verilog, System Verilog, UVM
  • Debugging pre-silicon verification failures
  • Customer-facing technical support

Nice-to-have

  • Proactive problem solving
  • Continuous learning and innovation
  • Building customer trust and relationships

Key Requirements

  • 8+ years of Design Verification Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • Experience with PCIe protocol is a must
  • CXL, UCIe, UALink, UEC protocols knowledge

Work Rights

Not specified

Tailored Resume

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