Physical Design Engineer - Soc

Samsung Semiconductor India Research (SSIR)

Bangalore, India
Complex soc top physical implementation
Synthesis place and route sta timing closure
Power user of icc dc pt vslp redhawk calibre
The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems

Job Summary

  • The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems.
  • Engineers will utilize industry-standard tools like ICC, DC, PT, and Calibre to achieve timing closure and PPA optimization.
  • Candidates must have a solid understanding of deep sub-micron designs including 8nm and 5nm process nodes.

Matching Summary

The role involves complex SOC top physical implementation for next-generation mobile application processors and modem subsystems.

Skills & Requirements

Must-have

  • Complex SOC top physical implementation
  • Synthesis Place and Route STA timing closure
  • Power user of ICC DC PT VSLP Redhawk Calibre
  • Experience with large SOC designs over 20M gates
  • Deep sub-micron design familiarity 8nm 5nm

Nice-to-have

  • Top level floor planning experience
  • Recent successful SOC tape-outs
  • Hierarchical and top-down design methodology
  • Strong scripting skills in Perl Tcl

Key Requirements

  • 5+ years of experience
  • B.Tech B.E M.Tech M.E degree
  • Expertise in block level and full-chip SDC cleanup

Work Rights

Not specified

Tailored Resume

Cover Letter